Split Write DRAM: Reducing DRAM Access Latency by Mitigating Read-Write Interference
Reading group: Soulayman Jbari presented "Split Write DRAM: Reducing DRAM Access Latency by Mitigating Read-Write Interference" (MemSys'25) at 1A312 the 23/1/2026 at 11h30.
Abstract
Modern memory controllers use a write queue to optimistically defer DRAM write operations until a rank is idle to avoid disrupting latency-critical reads. Unfortunately, when the write queue reaches capacity without adequate idle time available, all pending read operations suffer a severe performance penalty while waiting for the memory controller to perform a mandatory bus turnaround and drain the outstanding writes. To mitigate the performance impact of write draining, we introduce Split Writes, which divide write operations into two phases: Data Transfer and Row Access. Split Writes enable the memory controller to first transfer the write data to a small, fast buffer—called the Split Write Cache (SWC)—located within the DRAM chip during write draining. Data Transfer avoids row activation or precharge, significantly reducing the latency of write draining. Later, the memory controller can exploit bank idle time, which is more common than rank idle time, to opportunistically write data back from the split write caches to DRAM rows. Unlike prior techniques that delay writes or modify cache behaviour, Split Writes enable timely write draining while minimizing read disruption. Furthermore, Split Writes preserve protocol correctness, requiring modest architectural changes while improving system responsiveness under high write pressure.
