Toward Practical 128-bit General Purpose Microarchitectures
Invited talk: Chandana S. Deshpande presented "Toward Practical 128-bit General Purpose Microarchitectures" at 4A312 the 25/7/2024 at 14h00.
Abstract
The goal of this project is to build the next generation computer, which notably entails increasing the address space (e.g., to 128-bit) in order to allow any process to access a gigantic amount of data. This can notably allow the unification of storage and memory, allowing data to be accessed with load and store instructions regardless of it actual location (memory, storage, peripheral, etc.).
Within the processor, going to 128-bit has a significant impact. First, general purpose registers must double in size in order to implement 128-bit arithmetic to manipulate 128-bit addresses. This impacts the area and power consumption of the register file, the functional units, the bypass network, etc. This hardware overhead is paid even if a user simply ported (recompiled) a program written for a 64-bit machine to this new 128-bit machine, even if the program does not make use of the larger address space. Moreover, there exists a performance cost since pointers now occupy 128 bits, meaning that the footprint of pointers in memory (and in cache memory) is doubled. The goal of this thesis is to quantify the impact of the move from 64-bit to 128-bit on central processor (CPU) performance, and to propose microarchitectural solutions to significantly reduce this impact.
The focus of the presentation is to discuss this ongoing work by briefly introducing state-of-the art clustered microarchitectures, steering policies and to quantify the impact of the move from 64-bit to 128-bit on central processor (CPU) performance, and to propose microarchitectural solutions to significantly reduce this impact. The proposed microarchitecture is currently being implemented in gem5 simulator, which will further be discussed.
Bio
PhD Student - III Laboratoire TIMA Grenobl INP, Grenoble
